1. Field of the Invention
The invention relates in general to the fabrication of dynamic random access memories (DRAM), and more particularly to the fabrication of a DRAM capacitor to advance the surface area of a storage electrode in the capacitor and to enhance the useful area of the DRAM capacitor.
2. Description of the Related Art
When the functions of microprocessors are more and more powerful and the programs and operations executed by software are more and more colossal, the market for memory capacity is greater and greater. FIG. 1 is a schematic diagram showing a memory cell in DRAM devices. As shown, a memory cell comprises with a transistor 10 and a storage electrode 11, in which a source of the transistor 10 is coupled with a corresponded bit line 12, a gate of the transistor 10 is coupled with a word line 13 and a drain is coupled with the storage electrode 14 (or lower electrode 14) of the storage capacitor 11. A plate electrode 15 (or upper electrode 15 or cell electrode 15) of the storage electrode 11 is connected to a fixed voltage source, and there is a dielectric layer located between the storage electrode 14 and plate electrode 15.
A capacitor is the heart of the DRAM for information storage. If the charge stocked in the capacitor increase, the effect from noise when reading the information will be greater, for example, soft errors formed from .alpha. particles will drop the refresh frequency. Methods of enhancing the capacitance of a storage capacitor for stocking charge include: (1) adding the dielectric constant of a dielectric layer to increase the charge stocked in a unit area of a capacitor, (2) decreasing the thickness of a dielectric layer but then the quality of a dielectric thickness to a minimum, (3) adding the area of a capacitor to increase the charge stocked in the capacitor, but then integrating of DRAM decreases.
When the capacitance of a conventional DRAM is small, the process of integrated circuits is conducted by a two-dimensional capacitor, a planar-type capacitor. This planar-type capacitor needs to employ a large area of a semiconductor substrate for stocking, charge so it isn't applied at a high integration. A capacitor in a highly integrated DRAM needs to employ a three-dimensional structure, for example, a stacked-type capacitor or a trench-type capacitor. When the DRAM device is designed toward even higher integration, the simple three-dimensional structured capacitor isn't adequate. Thus methods of adding, surface area to capacitorwithin a limited scope in DRAM are used.
FIGS. 2A-2D show a method of fabricating a conventional trench-type capacitor structure. Referring to FIG. 2A, a substrate 200 is provided, on which at least a field oxide layer 201, a gate electrode 202, source/drain regions 203, 204 and 205 and a first insulating layer 206 covering the gate electrode 202 are formed. Then, a first polysilicon layer is formed and patterned by using photolithography techniques to form a bit line 207 coupling with the source/drain region 204. A second insulating layer 208 is deposited, and patterned to make the second insulating layer 208 covering the bit line 207 and exposing the source/drain region 205.
Referring to FIG. 2B, a first thin and doped polysilicon layer 209 is formed and coupled with the source/drain region 205. The first thin and doped polysilicon layer 209 is covered with a photoresist layer 210, and patterned to form a via 211. An oxide material 212 is filled into the via 211. The photoresist layer 210 is removed and a second thin and doped polysilicon layer 213 forms the structure shown in FIG. 2C. Referring to FIG. 2D, the second polysilicon layer 213 on the oxide material 212 is removed to expose the oxide material 212. Then, the oxide material 212 filled into the second polysilicon layer 213 is removed to form a storage electrode coupling with the source/drain region 204. After forming a dielectric layer on the storage electrode, a third doped polysilicon layer is provided to form a planar electrode. Then, the back-end processes which include forming a metal contact and a insulated defensive layer are performed to finish the DRAM structure.
FIG. 3 is a cross-sectional view of a conventional stacked-type DRAM capacitor structure. Referring to FIG. 3, first a semiconductor substrate 30 is provided, on which a metal oxide semiconductor transistor 32 (MOS) is formed. The MOS 32 comprises a gate electrode 33, a source/drain region 34 and a spacer 35. There are a field oxide layer 36 and an insulating layer 38 on the semiconductor substrate 30. A insulating layer 38 is deposited and etched at the site on the specific source/drain region 34 to form a contact. In sequence, a lower electrode 39, a dielectric layer 310 and an upper electrode 311 are provided on the contact to form a stacked-type capacitor 312. The dielectric layer 310 has a structure comprising a silicon nitride layer and a silicon oxide layer (NO), or comprising a silicon oxide layer, a silicon nitride layer and a silicon oxide layer (ONO). The lower electrode 39 and the upper electrode 311 are polysilicon layers, and the lower electrode 39 has a ragged surface. Last, the back-end processes which include forming a metal contact and a insulated defensive layer are performed to finish the DRAM structure.
Currently, a method of fabricating a DRAM capacitor is to improve a surface format of the capacitor by making several ragged surfaces. Although surface area is increased to enhance the capacitance, the degree of enhancement is limited. The method can't be used at higher capacitance or in smaller devices. Furthermore, the method has a complex process that repetitively uses, deposition and etching to form the required capacitor structure. This makes the process complicated and increases the cost.